Workshop Description
As of early 2026, the largest quantum processors operate in the 50-1,200 physical qubit range with two-qubit gate error rates between 10^-2 and 10^-3. These are noisy intermediate-scale quantum (NISQ) devices. They cannot run Shor's algorithm or any error-corrected algorithm at useful scale. The path to fault tolerance requires crossing the error correction threshold, implementing surface codes or alternatives at sufficient code distance, and scaling to millions of physical qubits. Different hardware approaches face different bottlenecks on this path.
This session examines each major qubit modality through the lens of what matters for defence: how quickly can this approach reach a cryptographically relevant quantum computer (CRQC), and what are the engineering obstacles remaining? Participants receive a vendor-neutral comparison of IBM, Google, IonQ, Quantinuum, PsiQuantum, Xanadu, QuEra, and Pasqal hardware roadmaps, alongside a framework for distinguishing peer-reviewed quantum advantage demonstrations from marketing claims. The session concludes with practical guidance on investment timing and procurement evaluation for defence organisations.
What participants cover
- Superconducting, trapped ion, photonic, and neutral atom qubit architectures with performance benchmarks
- Surface codes, colour codes, and LDPC codes: logical qubit overhead and fault-tolerance thresholds
- Magic state distillation cost and its dominance in quantum resource estimates
- Current hardware status: qubit counts, gate fidelities, and coherence times across vendors
- CRQC timeline scenarios and the engineering gaps that determine arrival dates
- TRL-based procurement framework for evaluating quantum computing vendor claims